Field of the Invention
The present invention relates to a method for evaluating an optical image of a pattern, a recording medium, and an information processing apparatus.
Description of the Related Art
An exposure apparatus is used in an exposure process during a process for manufacturing a semiconductor device. The exposure apparatus illuminates a mask (reticle) with a circuit pattern of the semiconductor device formed thereon by an illumination optical system using light from a light source, and transfers the pattern of the mask onto a wafer via a projection optical system or the like.
In recent years, further miniaturization of the pattern of the semiconductor device has been advancing, and a super-resolution technique, such as Off-Axis Illumination of the illumination optical system and an optical proximity effect correction (OPC) of the pattern of the mask, has started to be used in the exposure process.
The pattern corrected by the OPC is input into an optical image simulator, and an optical image of the pattern is calculated and then evaluated to confirm that this OPC has a desired correction effect. This is called lithography verification. The lithography verification can be carried out while the OPC is being performed or after the OPC is completed to determine whether a result of the correction is sufficiently excellent. When this lithography verification is carried out over an entire surface of a device chip (an entire surface of the mask), several days may be spent as a processing time, and it takes an enormous calculation time, since a data amount of the pattern is massive. Further, the miniaturization of the pattern has led to a further increase in the data amount of the pattern, and thus an increase in the time required for the lithography verification according thereto.
There is known a technique that conducts a rule-based check over an entire surface of a chip according to geometric design rules in advance, determines a pattern difficult to be resolved, and carries out the lithography verification on a region limited based on a result of this determination (U.S. Pat. No. 7,886,243).
The lithography verification discussed in U.S. Pat. No. 7,886,243 can reduce a region for which an optical image of a pattern is evaluated, and therefore can bring about a certain effect in a reduction in the calculation processing time. However, since this technique checks the entire surface of the mask according to the geometric design rules before the lithography verification, it takes a while to determine a critical pattern (a lithography hotspot). Further, a determination about a complicated graphic uses the geometric design rules therefor to also become complicated, which raises such a possibility that an oversight may occur in extraction of the critical pattern. This possibility cannot be ignored.